1. Field of the Invention
Generally, the present disclosure relates to the processing of wafers and to tools for the processing of wafers, and, more particularly, to methods and tools wherein a processing of a wafer and an inspection of a wafer are performed.
2. Description of the Related Art
Integrated circuits typically include a large number of circuit elements which include, in particular, field effect transistors. The circuit elements in an integrated circuit may be electrically connected by means of electrically conductive metal lines formed in a dielectric material, for example, by means of damascene techniques. The electrically conductive metal lines may be provided in a plurality of interconnect layers that are stacked on top of each other above a substrate in and on which the circuit elements are formed. Metal lines in different interconnect layers may be electrically connected with each other by means of contact vias that are filled with metal.
For the formation of integrated circuits, techniques of photolithography may be used. In a photolithography process, a pattern in a photomask (sometimes also denoted as a “reticle”) is projected to a layer of a photoresist that is provided over a wafer in an exposure tool, for example, a so-called scanner or stepper. The wafer may be a blank wafer, or it may include one or more integrated circuits in a stage of a manufacturing process. Portions of the photoresist are irradiated with actinic light, i.e., light that induces a chemical reaction in the photoresist by which the solubility of the photoresist in a subsequent development process is substantially changed, for example, ultraviolet light, which is used for projecting the pattern in the photomask to the photoresist. Other portions of the photoresist are not irradiated, wherein the pattern of irradiated portions of the photoresist depends on a pattern of photomask features provided on the photomask. This process may generally be referred to as an exposure process.
Thereafter, the exposed photoresist may be developed. Depending on whether a negative or a positive photoresist is used, and whether a negative or positive development process is used, in the development process, either the non-irradiated portions or the irradiated portions of the photoresist are dissolved in a developer and, thus, are removed from the wafer.
In some applications, several tools used for the wafer processing between the formation of the photoresist layer, which will be described in detail below, and the development of the photoresist may be integrated into larger units called integrated or lithographic or photolithographic tracks, or simply tracks, which may also include other tools like baking tools and/or exposure tools. The term “module” or “unit” is often used for a tool included in a track or a space within a track that substantially contains one tool.
After the formation of the developed photoresist layer, processes for patterning the wafer or modifying the electrical or chemical properties of the wafer may be performed using the portions of the photoresist remaining on the wafer as a photoresist mask. The processes for patterning the semiconductor structure may include one or more etch processes, wherein material is removed from portions of the wafer that are not covered by the photoresist mask. Thus, features can be formed on the wafer. The processes for modifying the electrical or chemical properties of the wafer may include one or more implantation processes, wherein ions are implanted into portions of the wafer that are not covered by the photoresist mask.
In the productive formation of integrated circuits, wafers may be processed in groups called lots, which may consist of about 1-25 wafers, for example, 12 or 25 wafers. Wafers of one lot may be processed substantially simultaneously and/or in immediate succession at each stage of the wafer production flow.
For forming a layer of a photoresist on a wafer, techniques of spin coating may be used. In spin coating, a photoresist solution that includes a photoresist and a solvent may be dispensed to a surface of a wafer that is mounted on a wafer chuck. Then, the photoresist solution may be distributed over the surface of the wafer by rotating the wafer. In some techniques of spin coating, the photoresist solution may be dispensed to the surface of the wafer while the wafer is stationary, and the rotation of the wafer may be started after the dispensing of the photoresist solution. Alternatively, the wafer may be rotated at a relatively low speed during the dispensing of the photoresist solution, and the wafer may be accelerated after the dispensing of the photoresist solution. The wafer may be rotated at a relatively high speed of rotation for an amount of time until a substantial amount of the solvent of the photoresist solution has evaporated and a solid layer of photoresist remains on the surface of the wafer.
In typical spin coating processes, only a fraction of the dispensed photoresist remains on the surface of the wafer. A substantial amount of the dispensed photoresist may be removed from the surface of the wafer during the spin coating process by centrifugal forces. Since photoresist solutions can be quite expensive, it may be of advantage to reduce the amount of photoresist solution that is dispensed to the surface of the wafer in the spin coating process. However, dispensing a too small amount of photoresist solution may lead to an insufficient wetting of the surface of the wafer by the photoresist solution. This may lead to an insufficient coating of the surface of the wafer with the photoresist layer so that the surface of the wafer has portions that are insufficiently covered by the photoresist layer. In typical spin coating processes, the minimum amount of photoresist solution required for forming a photoresist layer on a wafer is determined not by the thickness of the photoresist layer but by the amount of photoresist solution that is needed to wet the entire surface of the wafer.
A first sign of an amount of photoresist solution that is insufficient for wetting the whole surface of the wafer may be the occurrence of so-called “shark tooth” defects, which may include adhesion failures of the photoresist layer in outer regions of the wafer that extend radially outward to the edge of the wafer; in addition, such defects often (but not always) have a wedge shape. Names other than “shark tooth” are also in use in the industry for this defect type. To prevent the occurrence of such defects and other defects, and due to variations of the amount of photoresist solution that is actually dispensed on the surface of the wafer, as well as variations of the adhesion of the photoresist solution to the wafer, a safety margin is typically included into set values for the amount of photoresist solution that is dispensed to the surface of the wafer. The safety margin may be in a range from about 20-50% of the dispensed volume of the photoresist solution. Thus, providing the safety margin can substantially contribute to the amount of photoresist solution required and, accordingly, to material costs.
In the process of spin coating, other sorts of defects caused by other mechanisms may also occur, some of which may also extend to the edge of the wafer.
The applicability of spin coating is not limited to the formation of photoresist layers. Spin coating techniques may also be used for the formation of other material layers on wafer surfaces, for example, anti-reflective coatings, such as bottom anti-reflective coatings (BARCs) and top anti-reflective coatings (TARCs) which are provided below and above photoresist layers, respectively, immersion top coats, which may be formed over photoresist layers for protecting the photoresist from an immersion fluid used in immersion photolithography and vice versa, planarization and gap fill materials, spin-on hardmasks, for example hardmasks including spin-on carbon materials, some types of low-k interlayer dielectrics, and polyimides. In the application of spin coating techniques for the formation of such layers, issues similar to those described above may occur.
Furthermore, issues similar to those described above that are conventionally addressed by providing relatively large safety margins may occur in processes other than spin coating, wherein there is a critical threshold for an amount of material and/or a processing time, below which characteristic defects start to occur. Depending on the process, the characteristic defects may be different from the above-mentioned “shark tooth” defects. Examples of processes wherein there is a critical threshold for an amount of material and/or a processing time include processes of photoresist development, single wafer cleaning processes, rinse processes, pre-wetting processes, and/or wafer priming or adhesion promotion processes. In such techniques, providing relatively large safety margins for an amount of material that is used and/or for a processing time may substantially contribute to the material consumption and/or the processing time.
In the formation of integrated circuits, wafers may be inspected at different stages of the production flow, for example, after photolithography steps, to detect the presence of defects. If inspected wafers are found to have defects, the wafers and potentially other wafers that were processed in a similar way as the wafers with defects may be subjected to an additional rework process, wherein defective upper layers of the wafer may be removed and some previous processing steps may be repeated. If too many defects are found on too many wafers, one or more previous processing steps may be modified to reduce the occurrence of defects. Common inspection techniques include inspecting the whole wafer surface or a relatively large part of the wafer surface, since defects can usually occur at different locations on the wafer surface. Therefore, and because of the relatively high spatial resolution that may be required for the detection of defects, the inspection of a wafer with common inspection techniques usually takes significant time, for example, from about 1 minute to about 1 hour. As a consequence, it may be difficult to inspect all lots or all wafers of a lot at an inspection step, since this would slow down the production process too much and/or would require too many inspection tools, which are expensive. Thus, with common inspection techniques, there is a certain probability that wafers with defects escape detection, corresponding to the number of lots and/or wafers per lot which are sampled for inspection, and/or to the fraction of the wafer surface that is inspected in the inspection process.
In view of the above issues, the present disclosure provides methods and devices that may allow a reduction of amounts of materials used and/or a reduction of processing times while maintaining a relatively low likelihood of defects occurring, as well as methods and devices for efficiently inspecting wafers for defects resulting from insufficient amounts of materials and/or processing times and thus reducing the likelihood of such defects escaping detection.